Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program

ABSTRACT

A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-ntact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to semiconductor devices, a methodof designing semiconductor devices, and recording media for storingsemiconductor designing programs. In particular, the present inventionrelates to semiconductor devices having multi-layer wiring structure anda technique of designing a highly integrated semiconductor device havingfine metal wires connected through via-contacts provided withextensions.

[0003] 2. Description of the Related Art

[0004] Fine technology for semiconductor devices is rapidly improving toprovide very small circuit patters. The very small circuit patterns havea problem.

[0005] The problem is an optical proximity effect that occurs during alithography process even if masks or stepper for producing circuitpatterns are precise. The optical proximity effect rounds an end of ametal wire. If the rounded wire end is connected to a via-contact, itreduces or eliminates a contact area between the wire end and thevia-contact, to increases contact resistance between the wire and thevia-contact and cause an open defect.

[0006]FIG. 1 is a plan view showing a pattern of metal wires designedaccording to a prior art. Wires 53 and 54 are in an upper layer and areconnected to via-contacts 51 and 52, respectively. The via-contacts 51and 52 are connected to wires 55 and 56 that are in a lower layer. FIG.2 is a plan view showing metal wires manufactured according to thedesign of FIG. 1. FIG. 3 is a sectional view taken along a grid line V2of FIG. 2. In FIGS. 1 and 2, the distance between adjacent grid linesindicates a minimum distance by which adjacent metal wires in each layermust be separated from each other. In FIG. 1, an end of each wire issquare and is in contact with the whole surface of a via-contact A maskformed according to the design of FIG. 1 also has a square shape foreach wire end. During a lithography process, however, the opticalproximity effect rounds each end of the wires 53 and 54 as shown in FIG.2. The optical proximity effect may make the ends of the wires 53 and 54recede in the arrow directions of FIG. 3, to reduce contact areasbetween the wires 53 and 54 and the via-contacts 51 and 52. In FIG. 3,dotted lines indicate designed ends of the wires 53 and 54.

[0007] There is an OPC (optical proximity correction) technique toincrease a contact area between a metal wire end and a via-contact Thistechnique corrects wire ends when preparing data to make a mask Forexample, this technique provides a wire end with a supplementary fringethat extends in every direction around a via-contact FIG. 4 shows apattern of metal wires having supplementary fringes 58 and 59 to covervia-contacts 51 and 52 according to a prior art The pattern of FIG. 4 isuseful to form metal wires having no round ends and having propercontact areas between the wire ends and via-contacts.

[0008] The supplementary fringes 58 and 59, however, increase the widthof each wire at each via-contact greater than the width of the otherpart of the wire. It is necessary therefore, to separate the adjacentvia-contacts 51 and 52 from each other with a grid line H2 interposingbetween them. In addition, other wires or via-contacts must not bearranged on grid lines that are adjacent to the via-contacts 51 and 52,or the intervals of grid lines must be increased to accommodate thesupplementary fringes 58 and 59. These conditions deteriorate theintegration of metal wires in a semiconductor device.

[0009] The supplementary fringes also increase the quantity of designdata, extend a mask data preparation time, and elongate a semiconductordevice development time.

SUMMARY OF THE INVENTION

[0010] An object of the present invention is to provide a semiconductordevice that is highly integrated and minimizes contact defects betweenmetal wires and via-contacts, a method of designing such a semiconductordevice, and a recording medium storing a program for designing such asemiconductor device.

[0011] Another object of the present invention is to provide asemiconductor device involving a short development time, a method ofdesigning such a semiconductor device, and a recording medium storing aprogram for designing such a semiconductor device.

[0012] In order to accomplish the objects, a first aspect of the presentinvention provides a semiconductor device having a via-contact, a mainwire having an end connected to the via-contact, and an extensionextended in line with the main wire from the end of the main wire beyondthe via-contact, the width of the extension being equal to or narrowerthan the width of the main wire.

[0013] The “via-contact” is a conductive plug formed in an intermediatelayer between wiring layers in a semiconductor device of multi-layerwiring structure, to electrically connect metal wires of the upper andlower wiring layers to each other. The via-contact may have any planshape, such as a quadrate or a circle. The “main wire” is a metal wireto electrically connect functional blocks, elements, or externalterminals on a semiconductor chip. The “extension” is a metal wireextended from an end of the main wire and electrically connectedthereto. It is preferable that the extension is equal to the main wirein materials, manufacturing methods, and manufacturing processes. Theextension extends in line with the main wire, i.e., in the lengthdirection of the main wire and runs over the via-contact, unlike thesupplementary fringe of the prior art that extends in all dictionsaround a via-contact. The extension may have any plan shape, such as aquadrate or a circle.

[0014] According to the first aspect, the extension is extended in linewith the main wire from an end of the main wire beyond the via-contactwith the width of the extension being equal to or narrower than thewidth of the main wire. The optical proximity effect rounds only an endof the extension, and therefore, the end of the main wire is intact andis properly connected to the via-contact without bulging around thevia-contact. As a result, other main wires or via-contacts may bearranged on grid lines or on grid intersections in the vicinity of thevia-contact in question without violating design rules. This realizes ahighly integrated layout for a semiconductor device with denselyarranged wires and via-contacts.

[0015] A second aspect of the present invention provides a semiconductordevice having a via-contact, a main wire having an end connected to thevia-contact, and an extension orthogonally extended from the end of themain wire beyond the via contact, the width of the extension being equalto or narrower than the width of the main wire.

[0016] According to the second asp, the extension is orthogonallyextended from an end of the main wire beyond the via-contact with thewidth of the extension being equal to or narrower than the width of themain wire. The optical proximity effect rounds only ends of theextension, and therefore, the end of the main wire is intact and isproperly connected to the via-contact.

[0017] A third aspect of the present invention provides a method ofdesigning a semiconductor device having X wiring layers. The methodincludes the steps of arranging functional blocks and elements in a chiparea with the use of an automatic layout tool, and arranging main wiresin a layer N, main wires in a layer N+1, and via-contacts in the layer Nwith the use of the automatic layout tool, to connect the functionalblocks and elements to one another through the main wires andvia-contacts. The via-contacts in the layer N include:

[0018] (1) the via-contacts themselves to electrically connect the mainwires in the layer N to the main wires in the layer N+1;

[0019] (2) an extension formed in the layer N+1 on and beyond each ofthe via-contacts and extended from an end of a corresponding one of themain wires of the layer N+1 in line with the main wire, the width of theextension being equal to or narrower than the width of the main wire;and

[0020] (3) an extension formed in the layer N under and beyond each ofthe via-contacts and extended from an end of a corresponding one of themain wires of the layer N in line with the main wire, the width of theextension being equal to or narrower than the width of the main wire.

[0021] Here, X is a natural number and N is a natural number satisfying0<=N<=X−1. If N=0 then a wiring layer N is a substrate, and a wiringlayer N+1 is a first wiring layer. It is preferable that allvia-contacts in the wiring layers have the same characteristics as thosementioned above. Even if a designer provides the via-contact of theabove characteristics only for specific wiring layers of a semiconductordevice, the effect of the present invention will be demonstrated in thesemiconductor device. “In line with” means that the extension has placedfor wiring direction only in 0 degree direction and 180 degreedirection.

[0022] According to the third act each via-contact has extensions eachconnected to an end of a main wire. The optical proximity effect roundsonly the extensions, and therefore, the end of each main wire is intactand is properly connected to the via-contact An end of each main wire isnot widened around a via-contact, so that other main wires orvia-mntacts may be arranged on grid lines or on grid intersections inthe vicinity of the via-contact in question without violating designrules. This realizes a highly integrated layout for a semiconductordevice with densely arranged wires and via-contacts. Data forvia-contacts entered into an automatic layout tool may include data forthe extensions, so that there is no necessity to provide a main wirewith the extension as a supplementary fringe when preparing data to makea mask. This decrees the quantity of design pattern data, shortens amask data preparation time, and reduces a semiconductor devicedevelopment time.

[0023] A fourth aspect of the present invention provides a method ofdesigning a semiconductor device having X wiring layers. The methodincludes the steps of arranging functional blocks and elements in a chiparea with the use of an automatic layout tool, and arranging main wiresin a layer N, main wires in a layer N+1, and via-contact in the layer Nwith the use of the automatic layout tool, to connect the functionalblocks and elements to one another through the main wires andvia-ntacts. The via-contacts in the layer N include:

[0024] (1) the via-contacts themselves to electrically connect the mainwires in the layer N to the main wires in the layer N+1;

[0025] (2) an extension formed in the layerN+1 on and beyond each of thevia-contacts in contact with an end of a corresponding one of the mainwires of the layer N+1 and extended orthogonally to the main wire, thewidth of the extension being equal to or narrower than the width of themain wire; and

[0026] (3) an extension formed in the layer N under and beyond each ofthe via-contacts in contact with an end of a corresponding one of themain wires of the layer N and extended orthogonally to the main wire,the width of the extension being equal to or narrower than the width ofthe main wire. “Orthogonally to” means that the extension has placed forwiring direction only in 90 degree diction and 270 degree direction.

[0027] According to the fourth aspect, each via-contact has extensionseach connected to an end of a main wire. The optical proximity effectrounds only the extensions, and therefore, the end of each main wire isintact and is properly connected to the via-contact Data for via-contactentered into an automatic layout tool may include data for theextensions, so that there is no necessity to provide a main wire withthe extension as a supplementary fringe when preparing data to make amask. This decreases the quantity of design pattern data, shortens amask data preparation time, and reduces a semiconductor devicedevelopment time.

[0028] A fifth aspect of the present invention provides a recordingmedium for storing a program that is used to design a semiconductordevice having X wiring layers. The program includes the steps ofarranging functional blocks and elements in a chip area with the use ofan automatic layout tool, and arranging main wires in a layer N, mainwires in a layer N+1, and via-contacts in the layer N with the use ofthe automatic layout tool, to connect the functional blocks and elementsto one another through the main wires and via-contacts. The via-contactsin the layer N include:

[0029] (1) the via-contacts themselves to electrically connect the mainwires in the layer N to the main wires in the layerN+1;

[0030] (2) an extension formed in the layer N+1 on and beyond each ofthe via-contacts and extended from an end of a corresponding one of themain wires of the layer N+1 in line with the main wire, the width of theextension being equal to or narrower than the width of the main wire;and

[0031] (3) an extension formed in the layer N under and beyond each ofthe via-contacts and extended from an end of a corresponding one of themain wires of the layer N in line with the main wire, the width of theextension being equal to or narrower than the width of the main wire.

[0032] A sixth aspect of the present invention provides a recordingmedium for storing a program that is used to design a semiconductordevice having X wiring layers. The program includes the steps ofarranging functional blocks and elements on a chip with the use of anautomatic layout tool, and arranging main wires in a layer N, main wiresin a layer N+1, and via-contacts in the layer N with the use of theautomatic layout tool, to connect the functional blocks and elements toone another through the main wires and via-contacts. The via-contacts inthe layer N include:

[0033] (1) the via-contacts themselves to electrically connect the mainwires in the layer N to the main wires in the layer N+1;

[0034] (2) an extension formed in the layer N+1 on and beyond each ofthe via-contacts in contact with an end of a corresponding one of themain wires of the layer N+1 and extended orthogonally to the main wire,the width of the extension being equal to or narrower than the width ofthe main wire; and

[0035] (3) an extension formed in the layer N under and beyond each ofthe via-contacts in contact with an end of a corresponding one of themain wires of the layer N and extended orthogonally to the main wire,the width of the extension being equal to or narrower than the width ofthe main wire.

[0036] Other and further objects and features of the present inventionwill become obvious upon an understanding of the illustrativeembodiments about to be described in connection with the accompanyingdrawings or will be indicated in the appended claims, and variousadvantages not referred to herein will occur to one skilled in the artupon employing of the invention in practice.

BRIEF DESCRIPTION OF THE DRAWINGS

[0037]FIG. 1 is a plan view showing a pattern of metal wires designedaccording to a prior art;

[0038]FIG. 2 is a plan view showing a pattern of metal wires manufactureaccording to the pattern of FIG. 1;

[0039]FIG. 3 is a sectional view taken along a grid line V2 of FIG. 2;

[0040]FIG. 4 is a plan view showing metal wires and via-contacts withsupplementary fringes according to a prior art;

[0041]FIG. 5 is a plan view showing metal wires of a semiconductordevice according to a first embodiment of the present invention;

[0042]FIG. 6 is a sectional view taken along a grid line V2 of FIG. 5;

[0043]FIG. 7A is a sectional view taken along a grid line H3 of FIG. 5;

[0044]FIG. 7B is a sectional view taken along a grid line H1 of FIG. 5;

[0045]FIG. 8 is a plan view showing a method of designing asemiconductor device according to the first embodiment;

[0046]FIG. 9 is a sectional view taken along a grid line V2 of FIG. 8;

[0047]FIG. 10A is a sectional view taken along a grid line H3 of FIG. 8;

[0048]FIG. 10B is a sectional view taken along a grid line Hi of FIG. 8;

[0049]FIG. 11 is a perspective view showing a computer system forachieving the semiconductor device designing method of the firstembodiment;

[0050]FIG. 12 is a plan view showing metal wires of a semiconductordevice according to a second embodiment of the present invention;

[0051]FIG. 13 is a sectional view taken along a grid line V2 of FIG. 12;

[0052]FIG. 14A is a sectional view taken along a grid line H3 of FIG.12; and

[0053]FIG. 14B is a sectional view taken along a grid line H1 of FIG.12.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0054] Various embodiments of the present invention will be describedwith reference to the accompanying drawings. It is to be noted that thesame or similar reference numerals are applied to the same or similarparts and elements throughout the drawings, and the description of thesame or similar parts and elements will be omitted or simplified

[0055] First Embodiment

[0056]FIG. 5 is plan view showing metal wires of a semiconductor deviceaccording to the first embodiment of the present invention. Thesemiconductor device has via-contacts 1 and 2, main wires 3 to 6, andextensions 7 to 10. An end of each main wire is connected to acorresponding via-contact. Each extension is in line with acorresponding main wire, is connected to an end of the main wire, and isextended beyond the via-contact to which the main wire is connected. Thewidth of each extension is equal to or narrower than the width of thecorresponding main wire.

[0057] Via-contacts are conductive plugs formed in an intermediate layerbetween wiring layers in a semiconductor device of multi-layer wiringstructure, to electrically connect metal wires formed on the upper andlower wiring layers to each other. In FIG. 5, the via-contacts 1 and 2are arranged on a and that is used for a designing purpose. The distancebetween adjacent gad lines indicates a minimum distance by whichadjacent metal wires in each layer must be separated from each other. InFIG. 5, the grid includes vertical grid lines V1 to V4 and horizontalgrid lines H1 to H4. The via-contact 1 is arranged on a gridintersection V2-H3, and the via-contact 2 on a grid intersection V2-H1.Although the width of each via-contact in FIG. 5 is equal to the widthof a corresponding wire, it may be narrower than the wire width.Although each via-contact in FIG. 5 has a quadrate plan shape, it mayhave any other plan shape.

[0058] The main wires 3 to 6 are metal wires for electrically connectingfunctional blocks or elements of the semiconductor device to each otherto transmit signals or power among them. The main wire 3 is in a layerN+1 and is connected to the main wire 5, which is in a layer N, throughthe via-contact 1 that is in the layer N. The main wire 4 is in thelayer N+1 and is connected to the main wire 6, which is in the layer N,through the via-contact 2 that is in the layer N. The via-contacts 1 and2 are in contact with the ends of the main wires 3 to 6. The main wires3 to 6 are arranged on grid lines. According to the first embodiment,the semiconductor device consists of X wiring layers where “X” is anatural number and “N” is a natural number that satisfies 0<=N<=X−1. IfN=0 then a layer N is a substrate, and a layer N+1 is a first layer.Via-contacts that connect the wires of a layer N to the wires of a layerN+1 are in the layer N.

[0059] The extensions 7 to 10 are metal wires that may be rounded by theoptical proximity effect so that the ends of the main wires 3 to 6 areintact The extensions 7 to 10 are electrically connected to thecorresponding main wires. It is preferable that the extensions 7 to 10are equal to the main wires 3 to 6 in materials, manufacturing methods,and manufacturing processes. Each extension runs in line with thecorresponding main wire beyond the corresponding via-contact, unlike thesupplementary fringe of the prior art that spreads around a via-contact.Although the plan shape of each extension in FIG. 5 is quadrate, it mayhave any other shape such as a circle.

[0060] The extension 8 is in the layer N+1 and is extended from the endof the main wire 3. The extension 10 is in the layer N+1 and is extendedfrom the end of the main wire 4. The extension 7 is in the layer N andis extended from the end of the main wire 5. The extension 9 is in thelayer N and is extended from the end of the main wire 6. Although eachend of the main wires is on a via-contact in FIG. 5, this does not limitthe present invention. The main wires may have via-contacts in themiddle thereof. Such middle via-contacts may have no extensions.

[0061]FIG. 6 is a sectional view taken along a grid line V2 of FIG. 5.The end of the main wire 3 in the layer N+1 is on the via-contact 1 thatis in the layer N. Under the via-contact 1, there is the end of the mainwire 5 that is in the layer N. The end of the main wire 4 in the layerN+1 is on the via-contact 2 that is in the layer N. Under thevia-contact 2, there is the end of the main wire 6 that is in the layerN. The sectional view of FIG. 6 is in the wiring direction of the layerN+1, and therefore, shows that the extension 8 is extended from the endof the main wire 3 beyond the via-contact 1 and that the extension 10 isextended from the end of the main wire 4 beyond the via-contact 2.

[0062]FIG. 7A is a sectional view taken along a grid line H3 of FIG. 5,and FIG. 7B is a sectional view taken along a grid line H1 of FIG. 5.These sectional views are in the wiring direction of the 5 layer N, andtherefore, show that the extension 7 is extended from the end of themain wire S beyond the via-contact 1 and that the extension 9 isextended from the end of the main wire 6 beyond the via-contact 2.

[0063] A method of designing a semiconductor device according to thefirst embodiment will be explained.

[0064] (1) Step S1 employs a standard LSI automatic layout tool tocompactly arrange functional blocks and elements in a chip area withoutviolating design rules. At this time, wiring spaces are secured amongthe functional blocks and elements so that the functional blocks andelements may be connected to one another through metal wires.

[0065] (2) Step S2 employs the automatic layout tool to arrange mainwires and via-contacts in the wiring spaces so that main wires in layersN and N+1 are connected to each other through via-contacts in the layerN. These main wires serve to connect the functional blocks and elementsto one another or transmit signals to and from I/O pads.

[0066] Metal wires of a standard LSI are longitudinally or laterallyoriented layer by layer. Namely, each layer has a given orientation ofwires, and therefore, once a layer is given, the orientation of wires inthe given layer is automatically determined The via-contacts in thelayer N arranged by the automatic layout tool connect the main wires inthe layer N to the main wires in the layer N+1, and the orientations ofthese main wires are automatically determined Accordingly, step S2employs the automatic layout tool to arrange, together with thevia-contacts in the layer N, extensions that extend in line with themain wires in the layers N and N+1. As a result, the metal wiresprovided with the extensions are prepared as shown in FIG. 5. Namely,step S2 arranges the main wires in the layers N and N+1 and thevia-contacts in the layer N.

[0067]FIG. 8 is a plan view showing metal wires prepared according tothe semiconductor device designing method of the present invention. InFig, 8, via-contacts arranged in a layer N include:

[0068] (A) the via-contacts (1, 2) themselves to electrically connectmain wires in the layer N to main wires in a layer N+1;

[0069] (B) an extension (12, 14) formed in the layer N+1 on and beyondeach of the via-contacts and extended from an end of a corresponding one(3, 4) of the main wires of the layer N+1 in line with the main wire,the width of the extension being equal to or narrower than the width ofthe main wire; and

[0070] (C) an extension (11, 13) formed in the layer N under and beyondeach of the via-contacts and extended from an end of a corresponding one(5, 6) of the main wires of the layer N in line with the main wire, thewidth of the extension being equal to or narrower than the width of themain wire.

[0071] According to the first embodiment, the layer N includes thevia-contacts 1 and 2. On the via-contact 1, the extension 12 of thelayer N+1 extends from an end of the main wire 3 of the layer N+1 beyondthe via-contact 1. Under the via-contact 1, the extension 11 of thelayer N extends from an end of the main wire S of the layer N beyond thevia-contact 1. On the via-contact 2, the extension 14 of the layer N+1extends from an end of the main wire 4 of the layer N+1 beyond thevia-contact 2. Under the via-contact 2, the extension 13 of the layer Nextends from an end of the main wire 6 of the layer N beyond thevia-contact 2. The ends of the main wires 3 and 5 are connected to thevia-contact 1, and the ends of the main wires 4 and 6 are connected tothe via-contact 2.

[0072]FIG. 9 is a sectional view taken along a grid line V2 of FIG. 8.In FIG. 9, the extension 12 in the layer N+1 is on the via-contact 1 ofthe layer N, and the extension 11 in the layer N is under thevia-contact 1. The extension 14 in the layer N+1 is on the via-contact 2of the layer N, and the extension 13 in the layer N is under thevia-contact 2. Since the sectional view of FIG. 9 is in the wiringdirection of the layer N+1, the extensions 12 and 14 are protruding fromthe via-contacts 1 and 2, and there are no protrusions from theextensions 11 and 13. The right protrusion of the extension 12 is incontact with the main wire 3, and the left protrusion of the extension14 is in contact with the main wire 4. Consequently, the structure ofFIG. 9 is equivalent to that of FIG. 6.

[0073]FIG. 10A is a sectional view taken along a grid line H3 of FIG. 8,and FIG. 10B is a sectional view taken along a grid line Hl of FIG. 8.In FIG. 10A, the extension 11 in the layer N is under the via-contact 1of the layer N, and the extension 12 in the layer N+1 is on thevia-contact 1. In FIG. 10B, the extension 13 in the layer N is under thevia-contact 2 of the layer N, and the extension 14 in the layer N+1 ison the via-contact 2. The sectional views of FIGS. 10A and 10B are inthe wiring direction of the layer N, and therefore, show that theextensions 11 and 13 are protruding from the via-contacts 1 and 2 andthat there are no protrusions from the extensions 12 and 14. The leftprotrusion of the extension 11 is in contact with the main wire 5, andthe right protrusion of the extension 13 is in contact with the mainwire 6. Consequently, the structures of FIGS. 10A and 10B are equivalentto those of FIGS. 7A and 7B.

[0074] A program for executing the semiconductor designing method of thepresent invention may be stored in a computer readable recording medium.The recording medium is read by a computer system, which executes theprogram to achieve the semiconductor designing method of the presentinvention. The recording medium may be any medium capable of recordingprograms, such as a semiconductor memory, a magnetic disk, an opticaldisk a magneto-optic disk or a magnetic tape.

[0075]FIG. 11 is a perspective view showing a computer system 80 capableof reading a program from a recording medium, executing the program, andachieving the semiconductor designing method according to the program.The computer system 80 has a floppy disk drive 81 to receive a floppydisk 83, and a CD-ROM drive 82 to receive a CD-ROM 84. The floppy disk83 and CD-ROM 84 store programs, which are read by and installed in thecomputer system 80. An external drive 87 may be connected to thecomputer system 80 to handle a semiconductor ROM 85 or a magneticcassette tape 86, both storing programs.

[0076] According to the first embodiment, the extensions (7 to 10, or 11to 14) are formed in layers N and N+1 and are extended from ends of themain wires (3 to 6), which are in the layers N and N+1, beyond thevia-contacts (1 and 2) formed in the layer N. As a result, the opticalproximity effect rounds only the extensions, and no roundness occurs onthe ends of the main wires.

[0077] The extensions 8 and 10, or 12 and 14 formed in the layer N+1protrude from the via-contacts 1 and 2 toward the grid line 2, andtherefore, the main wires 5 and 6 must be arranged on the grid lines H3and H1, respectively, with the grid line H2 interposing between them.Even so, the main wires 5 and 6 are not widened at the via-contacts 1and 2, and therefore, other main wires may be arranged on the grid lineH2 in the layer N. Similarly, other main wires may be arranged on thegrid line H4 in the layer N.

[0078] Further, the main wires 3 and 4 are not widened at thevia-contacts 1 and 2, and therefore, other main wires may be arranged inthe layer N+1 on grid lines V1 and V3 that are adjacent to the grid lineV2 on which the main wires 3 and 4 are arranged.

[0079] Since the extensions 7 to 10, or 11 to 14 protrude from thevia-contacts 1 and 2, no via-contacts are allowed on three gridintersections V1-H1, V2-H2, and V3-H3. Since the extensions on thevia-contacts extend only in the wiring directions, grid-intersectionsV1-H2, V3-HZ V1-H4, and V3-H4 that are obliquely adjacent to the gridintersections V2-H1 and V2-H3 where the via-contacts 1 and 2 are set mayhave other via-contacts.

[0080] In this way, the first embodiment forms extensions in line withmain wires in each wiring layer of a semiconductor device. Theextensions extend from ends of the main wires beyond via-contacts towhich the main wires are connected. The width of each extension is equalto or narrower than the width of a corresponding main wire. The opticalproximity effect only rounds the extensions so that the ends of the mainwires may be left intact This prevents contact defects and open defectsbetween the main wires and the via-contacts. Each extension shows nowidening around a corresponding via-contact, and therefore, other mainwires or other via-contacts may be arranged in the vicinity of thevia-contact without violating design rules. Consequently, the firstembodiment is capable of densely arranging metal wires and via-contactsto realize a highly integrated wiring layout for a semiconductor device.The first embodiment may include data for extensions in data forvia-contacts to be entered into an automatic layout tool, so that thereis no necessity to provide a main wire with the extension as asupplementary fringe when preparing data to make a mask. This decreasesthe quantity of design pattern data, shortens a mask data preparationtime, and reduces a semiconductor device development time.

[0081] Second Embodiment

[0082] Unlike the first embodiment that arranges extensions in line withmain wires, the second embodiment arranges extensions orthogonally tomain wires. FIG. 12 is a plan view showing metal wires of asemiconductor device according to the second embodiment

[0083] The semiconductor device of the second embodiment has X wiringlayers where “X” is a natural number and “N” is any natural number thatsatisfies 0<=N <=X−1. If N=O then a layer N is a substrate,and a layerN+1 is a fist layer. Via-contacts that connect wires in a layer N towires in a layer N+1 are in the layer N. The semiconductor device of thesecond embodiment has via-contacts (1, 2), main wires (3 to 6) havingends connected to the via-contacts, and extensions (15 to 18)orthogonally extending from the ends of the main wires beyond thevia-contacts, the width of each extension being equal to or narrowerthan the width of a corresponding main wire.

[0084] The via-contacts 1 and 2 are formed in a layer N of thesemiconductor device, the main wires 3 and 4 are formed in a layer N+1,and the main wires 5 and 6 are formed in the layer N. The via-contacts 1and 2 and main wires 3 to 6 are the same as those of the firstembodiment, and therefore, will not be explained in detail.

[0085] The extension 16 is formed in the layer N+1 and is in contactwith an end of the main wire 3. The extension 18 is in the layer N+1 andis in contact with an end of the main wire 4. The extension 15 is in thelayerN and is in contact with an end of the main wire 5. The extension17 is in the layer N and is in contact with an end of the main wire 6.Although each end of the main wires is on a via-contact in FIG. 12, thisdoes not limit the present invention. The main wires may havevia-contact in the middle thereof. Such middle via-contacts may haveextensions that are orthogonal to the main wires. Although theextensions in FIG. 12 have each a quadrate plan shape, the plan shapethereof is optional, for example, a circle.

[0086]FIG. 13 is a sectional view taken along a grid line V2 of FIG. 12.The end of the main wire 3 in the layer N+1 is on the via-contact 1 thatis in the layer N, and the end of the main wire 5 in the layer N isunder the via-contact 1. The end of the main wire 4 in the layer N+1 ison the via-contact 2 that is in the layer N, and the end of the mainwire 6 is under the via-contact 2. The grid line V2 is orthogonal to thewiring direction of the wiring layer N, and on the grid line V2, thereare the via-contacts 1 and 2 where the ends of the main lines 5 and 6are present. In contact with the end of the main wire 5, the extension15 in the layer N extends beyond the via-contact 1. In contact with theend of the main wire 6, the extension 17 extends beyond the via-contact2.

[0087]FIG. 14A is a sectional view taken along a grid line H3 of FIG.12, and FIG. 14B is a sectional view taken along a grid line H1 of FIG.12. The grid line H3 is orthogonal to the wiring direction of the wiringlayer N+1, and on the grid line H3, there is the via-contact 1 that isin contact with the end of the main wire 3. In contact with the end ofthe main wire 3, the extension 16 extends beyond the via-contact 1. Thegrid line H1 is orthogonal to the wiring direction of the wiring layerN+1, and on the grid line Hi, there is the via-contact 2 that is incontact with the end of the main wire 4. In contact with the end of themain wire 4, the extension 18 extends beyond the via-contact 2.

[0088] Data for the extensions 15 to 18 may be included in data for thevia-contacts 1 and 2, so that an automatic layout tool may automaticallydesign a semiconductor device having metal wires provided with theextensions 15 to 18. Namely, the automatic layout tool may automaticallyarrange the main wires 3 to 6 in layers N and N+1 and the via-contactsin the layer N. In FIG. 12, the via-contacts in the layer N include:

[0089] (A) the via-contacts (1, 2) themselves to electrically connectthe main wires in the layer N to the main wires in the layer N+1;

[0090] (B) the extensions (16, 18) formed in the layer N+1 on and beyondthe via-contacts in contact with the ends of the main wires (3, 4) ofthe layer N+1, respectively, and extended orthogonally to the mainwires, the width of each extension being equal to or narrower than thewidth of the corresponding main wire; and

[0091] (C) the extensions (15, 17) formed in the layer N under andbeyond the via-contacts in contact with the ends of the main wires (5,6) of the layer N, respectively, and extended orthogonally to the mainwires, the width of each extension being equal to or narrower than thewidth of the corresponding main wire.

[0092] A program for designing the semiconductor device of the secondembodiment may be stored in a computer readable recording medium, likethe first embodiment The recording medium is read by a computer system,which executes the program to design the semiconductor device of thesecond embodiment Such a computer system may be the one shown in Fi& 11.

[0093] According to the second embodiment, extensions (15 to 18) areformed in layers N and N+1 of a semiconductor device and areorthogonally extended from the ends of main wires (3 to 6) formed in thelayers N and N+1 beyond via-contacts (1 and 2) formed in the layer N. Asa result, the optical proximity effect rounds only the extensions, andno roundness occurs on the ends of the main wires. This prevents contactdefects or open defects between the via-contacts and the main wires. Thesecond embodiment may include data for the extensions in data for thevia-contacts to be entered into an automatic layout tool, so that thereis no necessity to provide a main wire with the extension as asupplementary fringe when preparing data to make a mask. This deceasesthe quantity of design pattern data, shortens a mask data preparationtime, and reduces a semiconductor device development time.

[0094] In summary, the present invention provides a highly integratedsemiconductor device with minimized contact defects between metal wiresand via-contacts, a method of designing such a semiconductor device, anda computer readable recording medium storing a program that achieves thesemiconductor device designing method.

[0095] The present invention also provides a semiconductor deviceinvolving a short development time, a method of designing such asemiconductor device, and a recording medium storing a design programfor designing such a semiconductor device.

What is claimed is:
 1. A semiconductor device comprising: a via-contact;a main wire having an end connected to the via-contact; and an extensionextended from the end of the main wire beyond the via-contact, the widthof the extension being equal to or narrower than the width of the mainwire.
 2. The semiconductor device of claim 1, wherein: the extension isin line with the main wire.
 3. The semiconductor device of claim 1,wherein: the extension is orthogonal to the main wire.
 4. A method ofdesigning a semiconductor device having X (X being a natural number)wiring layers, comprising the steps of: arranging functional blocks andelements in a chip area with the use of an automatic layout tool;arranging main wires in a layer N (N satisfying 0<=N<=X−1), main wiresin a layer N+1, and via-contacts in the layer N with the use of theautomatic layout tool to connect the functional blocks and elements toone another through the main wires and via-contacts; and arrangingextensions that extend in line with the main wires in the layers N andN+1, together with the via-contacts in the layer N, with the use of theautomatic layout tool
 5. The method of claim 4, wherein the extensionsin the layer N include: the via-contacts themselves to electricallyconnect the main wires in the layer N to the main wires in the layerN+1; an extension formed in the layer N+1 on and beyond each of thevia-contacts and in contact with an end of a corresponding one of themain wires formed in the layer N+1, the width of the extension beingequal to or narrower than the width of the main wire; and an extensionformed in the layer N under and beyond each of the via-contacts and incontact with an end of a corresponding one of the main wires formed inthe layer N, the width of the extension being equal to or narrower thanthe width of the main wire.
 6. The method of claim 4, wherein: arrangingeach of the extensions formed in the layer N+1, that is in line with thecorresponding main wire and is extended beyond the correspondingvia-contact; and arranging each of the extensions formed in the layer N,that is in line with the corresponding main wire and is extended beyondthe corresponding via-contact
 7. The method of claim 4, wherein:arranging each of the extensions formed in the layer N+1, that isorthogonal to the corresponding main wire and is extended beyond thecorresponding via-contact; and arranging each of the extensions formedin the layer N, that is orthogonal to the corresponding main wire and isextended beyond the corresponding via-contact
 8. A recording medium forstoring a program that is used to design a semiconductor device having X(X being a natural number) wiring layers, wherein the program includesthe steps of: arranging functional blocks and elements in a chip areawith the use of an automatic layout tool; arranging main wires in alayer N (N satisfying 0<=N <=X−1), main wires in a layer N+1, andvia-contacts in the layer N with the use of the automatic layout tool,to connect the functional blocks and elements to one another through themain wires and via-contacts; and arranging extensions that extend inline with the main wires in the layers N and N+1, together with thevia-contacts in the layer N, with the use of the automatic layout tool.9. The recording medium of claim 8, wherein: arranging each of theextensions formed in the layer N+1, that is in line with thecorresponding main wire and is extended beyond the correspondingvia-contact and arranging each of the extensions formed in the layer N,that is in line with the corresponding main wire and is extended beyondthe corresponding via-contact
 10. The recording medium of claim 8,wherein: arranging each of the extensions formed in the layer N+1, thatis orthogonal to the corresponding main wire and is extended beyond thecorresponding via-contact and arranging each of the extensions formed inthe layer N, that is orthogonal to the corresponding main wire and isextended beyond the corresponding via-contact.